1. Field of the Invention
The present invention relates to the testing of memory devices within data processing systems in order to detect memory defects, and more particularly relates to techniques for detection of address decoder open faults in such memory devices.
2. Description of the Prior Art
It is known to provide data processing system incorporating memories with self-testing mechanisms, sometimes termed built-in self-test (BIST) mechanisms, such that when the memory devices have been fabricated they may conduct a self-test or series of self-tests to determine if there are any memory defects present that would indicate that the circuit should be rejected. It is important that memory circuits should be highly reliable and that defective circuits should be effectively identified. As memory sizes increase, the proportion of the die being taken up by the memory is also increasing and, furthermore, the high transistor density within memory means that the defect density of these memories is becoming increasingly significant.
There are various types of defect that can arise in a memory device, and typically different tests need to be performed for each of the various types of defect. In addition to the detection of errors in the cells of the memory array itself, errors may also occur in the circuit elements used to control access to the memory cells within the memory array. For example, one or more address decoders may be provided in association with the memory array to activate particular rows and/or columns of the memory array dependent on an address provided to such address decoders. An address decoder can potentially suffer from an address decoder open fault (ADOF). ADOFs are caused by open defects in the logic gates of the memory address decoders, and due to their sequential behaviour, cannot be mapped to the faults of the memory array itself.
Considering for example a row address decoder used to activate a word line in the memory array, in fault free row address decoder circuitry only one word line is expected to be active at any point in time and hence during a write operation the data the subject of the write operation should only be written to the relevant location in that activated word line. However, if an open fault defect exists in one of the transistors of the address decoder, then a situation can arise where, when a new address is provided to the address decoder, a previously selected word line is not de-selected when the new word line appropriate to the new address is activated, and accordingly two word lines may be simultaneously activated. As a result, the data value the subject of the new write access request may end up being written to two locations.
Further details of address decoder open faults are provided in the article “Detection of CMOS Address Decoder Open Faults with March and Pseudo Random Memory Tests” by J Otterstedt et al., IEEE International Test Conference 1998, Pages 53 to 62. As described therein, a basic algorithm for testing for an open fault in an address decoder is to write a data value D to one address, and then to write the inverse data value D to a different address, after which the contents at the original address are read to determine if that data is D or D. If the data at the original address is now D, that indicates the presence of an open fault in the address decoder.
Clearly the above process needs to be repeated multiple times to seek to thoroughly test for all possible open faults within the address decoder. One mechanism that may be used is to perform a single step test, where each iteration of the above-mentioned algorithm (i.e. two writes followed by a read) is performed in response to a specified test command identifying the required addresses, data, etc. However, such an approach requires a very large amount of testing time to perform all of the required tests, and involves the issuance of multiple commands to identify each single step test. An additional problem is how to identify the appropriate addresses to write to in order to thoroughly test all possible open faults in the address decoder.
In the earlier-mentioned article “Detection of CMOS Address Decoder Open Faults with March and Pseudo Random Memory Tests”, a more automated test procedure is described which uses linear feedback shift registers (LFSRs) to generate required address sequences. However, in accordance with the techniques described therein, different configurations of LFSRs are required dependent on the relative width of the address bits provided to the largest subaddress decoder to the overall address width (see cases 1 to 4 set out in section 4 of that paper). Indeed for the situation of case 4, namely where k≧(n+2)/2 it is indicated that no LFSR-based solution could be found that would produce the required address sequences. In the above equation, k is the width of the largest subaddress decoder (i.e. the largest of the row decoder or the column decoder), and n is the overall address width.
Accordingly, it would be desirable to provide an improved technique for performing the required test sequence to detect address decoder open faults in a memory device.